Paired processing unit architecture for improved microcontroller performance in multi-core processor
US12153464B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 27, 2023 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Mar 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture in which the cores of a multicore processor are paired together. An internal memory may be connected to the pair of cores via separate leads. The pair of cores can run at reversed clock phases. A clock generator may be responsible for generating a clock signal that can be provided as input to one core, and a signal inverter may be responsible for inverting the clock signal so as to generate an inverted clock signal that can be provided as input to the other core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.