Processor with macro-instruction achieving zero-latency data movement
US12153921B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Jun 28, 2021 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Jun 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an array processor to process array data in response to a set of macro-instructions. A macro-instruction in the set of macro-instructions performs loop operations, array iteration operations, and/or arithmetic logic unit (ALU) operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.