Techniques for acceleration of a prefix-scan operation
US12153932B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Dec 21, 2020 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Mar 26, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples include techniques for an in-network acceleration of a parallel prefix-scan operation. Examples include configuring registers of a node included in a plurality of nodes on a same semiconductor package. The registers to be configured responsive to receiving an instruction that indicates a logical tree to map to a network topology that includes the node. The instruction associated with a prefix-scan operation to be executed by at least a portion of the plurality of nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.