In-memory computing using SOT-MRAM
US12154609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Apr 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetoresistive memory cell includes a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer. The first magnetic tunnel junction and the second magnetic tunnel junction each are disposed on the metal layer; the metal layer is configured to pass write current, a projection line of an easy axis of the first magnetic tunnel junction on a plane where the metal layer is located forms a first angle against a direction of the write current, and a projection line of an easy axis of the second magnetic tunnel junction on the plane where the metal layer is located forms a second angle against a direction opposite to the direction of the write current; the first angle and the second angle are all less than 90°; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass read current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.