Semiconductor device having a non-voltaile memory with high speed-read operation
US12154614B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Sep 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a memory cell array including a plurality of memory cells, a bit line selection circuit, including a first main select transistor, and a plurality of first sub-select transistors connected in parallel with each other, and the plurality of first sub-select transistors configured to be the first memory cell through the first bit line to transfer the read current from the first bit line to the first memory cell; and a sense amplifier configured to compare a reference current having a predetermined current value with a memory current drawn by the first memory cell, and output an output signal based on an input voltage, the sense amplifier including an active load, connected to the first main select transistor, comprising a PMOS diode or a NMOS diode configured to lower the input voltage at a sense node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.