Multi-time programmable non-volatile memory cell and memory with low power-cost
US12154629B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2023 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Aug 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-time programmable non-volatile memory cell includes: a deep N-well, and first, second, third P-wells or a first N-well located in parallel to each other in the deep N-well, where a control capacitor and a tunneling capacitor are located in the first P-well and the second P-well, respectively, and each of the control capacitor and the tunneling capacitor includes one or two N-type coupling regions in the P-well; one floating-gate transistor is located in the third P-well or the first N-well, the floating-gate transistor including a polysilicon floating gate and its underlying gate oxide; and the floating gate of the floating-gate transistor and its gate oxide extend along a direction perpendicular to the parallel P-wells to cover the control capacitor and the tunneling capacitor, respectively forming an upper plate and a gate oxide of the control capacitor and the tunneling capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.