Memory programming techniques to reduce power consumption
US12154635B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Aug 24, 2021 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Nov 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.