Method and device for correcting errors in resistive memories
US12154647B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Dec 7, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Jun 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A solution for improving the correction of errors in a 2T2R resistive memory protected by an error correction code. A method that makes it possible, through 1T1R read operations, to identify, in a codeword stored in memory, bits liable to be incorrect, called “erasures”, and then to invert these bits in the stored codeword in order to generate a new word corrected by the ECC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.