Transistor, ternary inverter comprising same, and transistor manufacturing method
US12154950B2 · kind B2 · utility
0Cited by
5References
12Claims
0Family size
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Key dates
| Filing date | Nov 19, 2020 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | May 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a transistor including: a constant current formation layer; a channel layer provided on the constant current formation layer; a pair of source/drain regions spaced apart from each other, with the channel layer therebetween on the constant current formation layer; a gate electrode provided on the channel layer; and a gate ferroelectric film provided between the gate electrode and the channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.