Dynamic assignment with phase-preserving clipping technique for digital transmitters and power amplifiers
US12155522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2023 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Apr 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/0028
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transmitter includes a first digital-to-analog converter (DAC) circuit consisting of a first set of unary cells to mix a first set of digital input data with a first clock signal. A second DAC circuit includes a second set of unary cells to mix a second set of digital input data with a second clock signal. A third circuit provides signals to the first DAC circuit and the second DAC circuit to implement an assignment scheme to assign either an in-phase (I) component or a quadrature (Q) component to the first set of unary cells and the second set of unary cells. Based on the assignment scheme, the first set of digital input data include I-data and Q-data, and the second set of digital input data include I-data and Q-data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.