Processor with block cipher algorithm, and a data encryption and decryption method operated by the processor
US12155751B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Jan 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/80
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processor with a block cipher algorithm and a data encryption and decryption method operated by the processor are shown. The processor uses a register to store an input key pointer pointing to an input key. In response to one single block cipher instruction of an instruction set architecture (ISA), the processor obtains input data from a first system memory area, performs the block cipher algorithm on the input data based on the input key indicated by the input key pointer stored in the register to encrypt or decrypt the input data to generate output data, and stores the output data in a second system memory area, or an internal storage area within the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.