Array substrate, display panel and display device
US12156442B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 31, 2020 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Jul 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/029
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display area of the array substrate only includes first sub-pixels capable of emitting light. In each two adjacent rows of first sub-pixels, a gate line electrically connected to one row of the plurality of rows of first sub-pixels and a reset signal line electrically connected to another row of the plurality of rows of first sub-pixels are electrically connected to the same first gate drive circuit. A target line electrically connected to a first row of the plurality of rows of first sub-pixels (i.e., another line other than the line electrically connected to the first gate drive circuit) is electrically connected to a second gate drive circuit. A target line electrically connected to a last row of the plurality of rows of first sub-pixels (i.e., another line other than the line electrically connected to the first gate drive circuit) is electrically connected to a third gate drive circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.