Patent · US Active

Mains monitoring

US12158483B2 · kind B2 · utility

0Cited by
2References
20Claims
0Family size

Assignee

Inventor

Key dates

Filing dateNov 9, 2022
Grant dateDec 3, 2024
Priority date
Expiry dateMar 31, 2043

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R27/14
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

In accordance with an embodiment, an integrated circuit chip includes a first input configured to receive a rectified potential and a second input configured to receive a reference potential; a first circuit configured to maintain the rectified potential at a constant value on the first input; a second circuit having a power supply input coupled to the first node; a first resistor series-connected to the first circuit between the second input and the first node, or connected between the first input and the first node; a third circuit connected across the first resistor and configured to deliver a signal which is an image of a current in the first resistor; and a fourth circuit configured to determine a mains frequency and/or a mains voltage based at least on the signal which is the image of the current in the first resistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.