Intelligent exposure of hardware latency statistics within an electronic device or system
US12158795B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2022 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Feb 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/16
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.