Instruction set architecture for neural network quantization and packing

US12159140B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Srijesh Sudarsanan · Waltham, US
• Deepak Mathew · Wilmington, US
• Marc Hoffman · Mansfield, US
• Sundar Balasubramanian · Chandler, US
• Mansi Jain · San Jose, US
• James G. Lee · Aiken, US
• Gerald T. Sweeney · Federal Way, US

Key dates

• Filing date: Apr 28, 2022
• Grant date: Dec 3, 2024
• Expiry date: May 3, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/082
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An electronic device receives a single instruction to apply a neural network operation to a set of M-bit elements stored in one or more input vector registers to initiate a sequence of computational operations related to a neural network. In response to the single instruction, the electronic device implements the neural network operation on the set of M-bit elements to generate a set of P-bit elements by obtaining the set of M-bit elements from the one or more input vector registers, quantizing each of the set of M-bit elements from M bits to P bits, and packing the set of P-bit elements into an output vector register. P is smaller than M. In some embodiments, the neural network operation is a quantization operation including at least a multiplication with a quantization factor and an addition with a zero point.