Concurrent memory access operations
US12159664B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2019 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Dec 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.