Multi-chip packaged semiconductor device
US12159818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2022 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Aug 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device is provided, including a first semiconductor die on which a first electrical component is integrated that includes a first terminal at a first surface of the first die and a second terminal at a second surface of the first die, a second semiconductor die similar to the first die, with a first surface of the second die facing the first surface of the first die. A first conductive element on the second surface of the first side electrically connected to the second terminal of the first electrical component, a second conductive element is on the second surface of the second die electrically connected to the second terminal of the second electrical component, and a third conductive element between the first surfaces of the first and the second die. The first terminals of the first and second electrical components are electrically connected through the third conductive element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.