Quantum circuit, quantum chip, and quantum computer
US12160233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2023 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Dec 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N69/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A quantum circuit, a quantum chip, and a quantum computer. The quantum circuit includes qubits, adjacent qubits being coupled, and each of the qubits including: a first capacitor, a first end of the first capacitor being grounded; a second capacitor, a first end of the second capacitor and the first end of the first capacitor being commonly grounded; and a first device, including a first squid and a third capacitor that are connected in parallel, wherein parallel-connected first ends of the first squid and the third capacitor are connected to a second end of the first capacitor, and parallel-connected second ends of the first squid and the third capacitor are connected to a second end of the second capacitor. According to the present disclosure, parameters of at least one of a plurality of capacitors in a qubit circuit can be adjusted, so that the design of the capacitor is more flexible and less spatially limited, which facilitates design and layout of other circuit structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.