Timestamp alignment for multiple nodes
US12160495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2021 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Jun 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0667
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.