Reference clock switching in phase-locked loop circuits
US12160497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2023 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Jan 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.