Storage device including mapping memory and method of operating the same
US12164376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Jan 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.