Double ring cache architecture
US12164424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2023 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Jul 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/465
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A distributed cache apparatus includes storage comprising a range of stored data and a processing device. A first cache level of the storage is segmented into a plurality of first data sub-ranges of the range of stored data, and each of the first data sub-ranges is associated with one of a first subset of a plurality of node devices. A second cache level of the storage is segmented into a plurality of second data sub-ranges of the range of stored data, and each of the second data sub-ranges is associated with one of a second subset of the node devices. Each of the second data sub-ranges is smaller than each of the first data sub-ranges. The processing device is configured to process a read request for data within the range of stored data by accessing one of the second subset of the node devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.