Vector dataflow architecture for embedded systems
US12164926B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Oct 13, 2021 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Jan 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a highly energy-efficient architecture targeting the ultra-low-power sensor domain. The architecture achieves high energy-efficiency while maintaining programmability and generality. The invention introduces vector-dataflow execution, allowing the exploitation of the dataflows in a sequence of vector instructions and to amortize instruction fetch and decode over a whole vector of operations. The vector-dataflow architecture allows the invention to avoid costly vector register file accesses, thereby saving energy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.