Hardware implementation of a deep neural network with variable output data format
US12165045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2018 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Oct 11, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware implementations of DNNs and related methods with a variable output data format. Specifically, in the hardware implementations and methods described herein the hardware implementation is configured to perform one or more hardware passes to implement a DNN wherein during each hardware pass the hardware implementation receives input data for a particular layer, processes that input data in accordance with the particular layer (and optionally one or more subsequent layers), and outputs the processed data in a desired format based on the layer, or layers, that are processed in the particular hardware pass. In particular, when a hardware implementation receives input data to be processed, the hardware implementation also receives information indicating the desired format for the output data of the hardware pass and the hardware implementation is configured to, prior to outputting the processed data convert the output data to the desired format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.