Semiconductor device
US12165702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Feb 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.