Semiconductor memory device and method of controlling the same
US12165708B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Jun 23, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises: a semiconductor layer extending in a first direction; a first and second conductive layer facing the semiconductor layer from one side and the other side in a second direction; and a charge storage layer comprising portions provided between the semiconductor layer and first conductive layer and between the semiconductor layer and second conductive layer. The semiconductor memory device is configured to execute erase operation, first write operation, and second write operation. In the first write operation, the first and second conductive layers are applied with first program voltage. In the second write operation, the first conductive layer is applied with second program voltage, and second conductive layer is applied with second voltage lower than the second program voltage. The second write operation is executed after execution of the erase operation and before execution of the first write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.