Nonvolatile memory device and operation method of detecting defective memory cells
US12165721B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Jan 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.