Non-volatile memory circuit and method
US12165722B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Aug 10, 2023 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Aug 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a bank of non-volatile memory (NVM) devices, a high-voltage (HV) driver, a global HV power switch configured to generate a HV power signal, and a HV power switch coupled between the global HV switch and the HV driver. The HV power switch is configured to, responsive to the HV power signal, output power and ground signals, each of the power signal and the ground signal having first and second voltage levels, and the HV driver is configured to output a HV activation signal to a column of the bank of NVM devices responsive to the power signal and the ground signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.