Chip form ultracapacitor
US12165808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2023 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | May 3, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/13
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An energy storage apparatus suitable for mounting on a printed circuit board using a solder reflow process is disclosed. In some embodiments, the apparatus includes: a sealed housing body (e.g., a lower body with a lid attached thereto) including a positive internal contact and a negative internal contact (e.g., metallic contact pads) disposed within the body and each respectively in electrical communication with a positive external contact and a negative external contact. Each of the external contacts provide electrical communication to the exterior of the body, and may be disposed on an external surface of the body. An electric double layer capacitor (EDLC) (also referred to herein as an “ultracapacitor” or “supercapacitor”) energy storage cell is disposed within a cavity in the body including a stack of alternating electrode layers and electrically insulating separator layers. An electrolyte is disposed within the cavity and wets the electrode layers. A positive lead electrically connects a first group of one or more of the electrode layers to the positive internal contact; and a negative lead electrically connects a second group of one or more of the electrode layers to the neg…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.