Array substrate and display panel including stacked metal layer test unit area
US12166044B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 25, 2020 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Sep 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The array substrate is provided and includes a substrate, a test unit area, first and second flat layers and a terminal area including an input and output terminal areas, the input terminal area includes input terminals for connecting input pins of a driving chip, and the output terminal area includes output terminals for connecting output pins of the driving chip, and each of the input and output terminals includes a second metal layer and a third metal layer disposed on a side of the second metal layer away from the substrate; the second flat layer on a side of the third metal layer away from the substrate and covering edges of the third metal layer; a surface of the first flat layer away from the substrate is not higher than a surface of the second flat layer away from the substrate, in a thickness direction of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.