Trench field effect transistor structure comprising epitaxial layer and manufacturing method thereof
US12166109B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2019 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Sep 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/2527
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a trench field effect transistor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate (100), forming an epitaxial layer (101), forming a device trench (102) in the epitaxial layer, and forming a shielding dielectric layer (107), a shielding gate layer (105), a first isolation dielectric layer (108), a gate dielectric layer (109), a gate layer (110), a second isolation dielectric layer (112), a body region (114), a source (115), a source contact hole (118), a source electrode structure (122), and a drain electrode structure (123). During manufacturing of a trench field effect transistor structure, a self-alignment process is adopted in a manufacturing process, so that a cell pitch is not limited by an exposure capability and alignment accuracy of a lithography machine, to further reduce the cell pitch of the device, improve a cell density, and reduce a device channel resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.