Gate structure and semiconductor device having the same
US12166126B2 · kind B2 · utility
0Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Oct 20, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.