Method, unit and circuit for implementing Boolean logic based on computing-in-memory transistor
US12166481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2023 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Aug 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method, a unit and circuits for implementing Boolean logics based on computing-in-memory transistors. The method is implemented by using the characteristics and the read-write mode of the computing-in-memory transistor; the basic unit consists of a computing-in-memory transistor and a pull resistor; the pull resistor in the basic unit is connected in series with the transistor, and the gate of the transistor is independent; the basic units can implement sixteen Boolean logic operations through different circuit structures and voltage configuration schemes. Compared with the logic circuit structure of the conventional CMOS transistors, the present disclosure can implement more logic operations with fewer transistors, which greatly optimizes circuit density and computing speed caused by data transmission between storage units and process units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.