Controlling duty cycle distortion with digital circuit
US12166490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | May 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method controls duty cycle distortion of clock signals. An electronic device obtains an input clock signal having a first frequency and a sampling clock signal having a second frequency that is lower than the first frequency. The sampling clock signal has a random noise distribution. The sampling clock signal is applied to sample high voltage duty cycles and low voltage duty cycles of the input clock signal for a duration of time to obtain a sampling result. The electronic device determines a duty cycle distortion level of the input clock signal in the duration of time based on the sampling result. A duty cycle control signal is generated based on the duty cycle distortion level to control the high voltage duty cycles of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.