Analog-to-digital converting circuit for decreasing decision delay and operation method thereof
US12167158B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Feb 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/709
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converting circuit includes a first amplifier configured to output a first output signal by comparing a pixel signal output from a pixel array with a ramp signal, and a second amplifier configured to generate a second output signal based on the first output signal. The second amplifier includes a first transistor configured to provide a power supply voltage to a first output node in response to the first output signal, a second transistor connected with a capacitor through a bias node, wherein the second transistor is configured to turn on in response to an auto-zero signal, a current source connected with the first transistor through the first output node, the current source configured to generate a power current based on a voltage level of the bias node, and a third transistor connected with the current source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.