Mask structure, semiconductor structure and manufacturing method
US12167584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2021 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | May 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a mask structure includes: patterning a sacrificial layer and a second dielectric layer, so as to form pattern structures each including a first pattern and a second pattern, and a width of a lower portion of the pattern structures is less than a width of a upper portion of the pattern structures; forming an initial mask pattern on sidewalls of each of the plurality of pattern structures; filling a first filling layer between adjacent initial mask patterns located on the sidewalls of different pattern structures; removing the second patterns and the initial mask pattern located on sidewalls of each of the plurality of second patterns; removing the first filling layer and the first patterns, so as to form first mask patterns; and forming second mask patterns on the first mask patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.