Array substrate and display apparatus
US12167648B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 17, 2020 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Dec 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/122
Abstract
An array substrate is provided. The array substrate includes a gate line extending along a first direction. The gate line includes a plurality of wide portions and a plurality of narrow portions respectively arranged along the first direction, the plurality of wide portions having a first dimension greater than a second dimension of the plurality of narrow portions along a second direction, the second direction at an angle in a range of 80 degrees to 100 degrees with respect to the first direction. An orthographic projection of a respective one of the plurality of wide portions in the respective subpixel on the base substrate overlaps with an orthographic projection of a portion of the semiconductor material layer in the respective subpixel on the base substrate, forming an active layer of the data-write transistor in the respective subpixel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.