Clock generating circuit and method for trimming period of oscillator clock signal
US12169419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2022 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Mar 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock generating circuit includes an oscillator, a clock counter, a finite state machine, and a non-volatile memory. The oscillator outputs an oscillator clock signal having a period based on a trim value. The clock counter counts the oscillator clock signal for a reference time. The finite state machine obtains the count value of the counted oscillator clock signal from the clock counter, and in a test mode, compares the count value with a target count value and changes the trim value based on the comparison result and determines a final trim value based on the changed trim value. The non-volatile memory stores the final trim value that is determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.