Memory test circuit, memory array, and testing method of memory array
US12170123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2022 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Jan 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.