Data receiving circuit, data receiving system and storage device
US12170129B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2022 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Mar 12, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data receiving circuit includes: a first amplification module configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a first sampling clock signal, and output a first voltage signal and a second voltage signal; a decision feedback control module configured to generate a second sampling clock signal in response to the enable signal; a decision feedback equalization module configured to, when the enable signal is in a first level value interval, perform decision feedback equalization in response to the second sampling clock signal and stop performing the decision feedback equalization when the enable signal is in a second level value interval; and a second amplification module configured to process the first voltage signal and the second voltage signal and output the first output signal and the second output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.