Patent · US Active

Accelerating low-density parity-check decoding via scheduling, and related devices, methods and computer programs

US12170529B1 · kind B1 · utility

0Cited by

2References

12Claims

0Family size

Assignee

NOKIA SOLUTIONS AND NETWORKS OY · FI

Inventors

Jonathan Ling · New Brunswick, US
Paul Cautereels · Hingene, BE

Key dates

Filing date	May 24, 2024
Grant date	Dec 17, 2024
Priority date	—
Expiry date	May 24, 2044

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/3961
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Devices, methods and computer programs for accelerating low-density parity-check (LDPC) decoding via scheduling are disclosed. At least some of the example embodiments described herein may allow reducing cost and improving power efficiency beyond that of semiconductor processor scaling currently used in accelerating LDPC decoding.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.