Method for checking DFT circuit, test platform, storage medium and test system
US12174250B2 · kind B2 · utility
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9References
16Claims
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Key dates
| Filing date | Feb 1, 2023 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jul 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/54
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for checking a Design for Test (DFT) circuit includes: transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, with the DFT circuit being configured to sequentially select multiple address latches according to the control signal to output the test mode signals; analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error; and outputting a simulation result report.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.