Method for manufacturing a mixed layer comprising a silicon waveguide and a silicon nitride waveguide
US12174425B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 6, 2021 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Nov 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B2006/12061
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A fabricating process may include: producing a trench, in an encapsulated-silicon layer, in the location where a silicon-nitride core of the waveguide must be produced; then depositing a silicon-nitride layer on the encapsulated-silicon layer, the thickness of the deposited silicon-nitride layer being sufficient to completely fill the trench; then removing the silicon nitride situated outside of the trench to uncover an upper face with which the trench filled with silicon nitride is flush; then depositing a dielectric layer that covers the uncovered upper face in order to finalize the encapsulation of the silicon-nitride core and thus to obtain a mixed layer containing both the silicon and silicon-nitride cores encapsulated in dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.