Patent · US Active

FSM based clock switching of asynchronous clocks

US12174659B2 · kind B2 · utility

0Cited by
4References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 25, 2022
Grant dateDec 24, 2024
Priority date
Expiry dateJan 13, 2043

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F1/324
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.