Fault tolerant disaggregated memory
US12174701B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 6, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | May 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/1097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure are directed to a low-latency, low-overhead fault tolerant remote memory framework, which packs similar-size in-memory objects into individual page-aligned spans and applies erasure coding on these spans. The framework fully utilizes efficient one-sided remote memory accesses (RMAs) to swap spans in and out using minimal network input/outputs (I/Os), with compaction techniques that reduce remote memory fragmentation. The framework can achieve lower tail latency and higher application performance compared to other fault tolerance solutions, at the cost of potentially more memory usage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.