Method for processing memory device
US12174737B2 · kind B2 · utility
0Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2024 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Mar 13, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/049
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of processing a NAND flash memory device including at least one NAND flash memory and a memory controller configured to control the at least one NAND flash memory. The method includes etching a portion of a first substrate of the NAND flash memory device to expose a wire connecting the at least one NAND flash memory and the memory controller to each other, dividing the wire into a first wire and a second wire by etching a first area of the etched first substrate, and connecting, to a second substrate, the first wire to which the at least one NAND flash memory is connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.