Methods and apparatus for transferring data within hierarchical cache circuitry

US12174753B2 · kind B2 · utility

Assignee

• Arm Limited · GB

Inventors

• Joseph Michael Pusdesris · Austin, US
• Klas Magnus Bruce · Leander, US
• Jamshed Jalal · Austin, US
• Dimitrios Kaseridis · Austin, US
• Gurunath Ramagiri · Austin, US
• Ho-Seop Kim · Gimhae-si, KR
• Andrew John Turner · Cambridge, GB
• Rania Hussein Hassan Mameesh · Cambridge, GB

Key dates

• Filing date: Nov 18, 2021
• Grant date: Dec 24, 2024
• Expiry date: Dec 21, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/1016
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.