Hardware-accelerated computing system
US12175283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2021 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jul 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a hardware-accelerated computing systems, calls are made from a processor to an accelerator core. The hardware-accelerated computing system includes a processor core having a stack, an accelerator, and an accelerator scheduler. The computing system is configured to process an accelerator command by the processor core issuing an accelerator command to the accelerator scheduler during execution of a task the accelerator scheduler receiving the accelerator command and requesting data from the stack, the processor sending the requested data from the stack to the accelerator scheduler, the accelerator scheduler sending the requested data to the accelerator and sending a write response to the processor, the accelerator processing the accelerator command, and the processor continuing execution of the task. The processor pauses execution of the task upon issuing the accelerator command and resumes execution of the task upon receiving the write response from the accelerator scheduler.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.