Wordline system architecture supporting erase operation and I-V characterization
US12176053B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2021 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jul 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.