Data receiving circuit, data receiving system, and memory device
US12176055B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Mar 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The data receiving circuit includes: a first amplification module configured to: receive a data signal, a first reference signal, and a second reference signal; and when an enable signal is at a first level, in response to a sampling clock signal and on a basis of a feedback signal, select the data signal and the first reference signal for first comparison and output a first signal pair, or select the data signal and the second reference signal for second comparison and output a second signal pair; and a second amplification module configured to receive output signals of the first amplification module as an input signal pair, perform amplification processing on a voltage difference of the input signal pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.